Since the introduction of integrated circuitry some decades ago, integrated circuit technology has progressed steadily to provide continually increasing integrated circuit density and speed, while lowering power consumption. As a result, extremely complex integrated circuit designs have become possible, sometimes including up to millions of transistors. There is no indication that this trend towards higher density and speed in integrated circuits will abate, or reverse, at any time in the foreseeable future.
As the ability to increase logic capacity (density) of modern integrated circuitry has grown, so has the complexity of modern logic designs. Associated with such increased logic complexity and logic density, however, is a similar increase in interconnection density (i.e., the interconnections between logic elements on an integrated circuit chip.) Generally, the greater the number of logic elements which are employed in a logic design, the greater the number of logic signals which interconnect them. These interconnections can often occupy large areas on an integrated circuit die (semiconductor die), particularly when large busses and complex logic blocks are employed in the design of the integrated circuit.
In attempting to improve interconnection efficiency, designers will often employ multiplexing techniques or large parallel busses between logic blocks. FIG. 1a and 1b are representative of these techniques.
FIG. 1a is a block diagram of a multiplexed circuit 100a therein three logic blocks 110a (LOGIC BLOCK #1), 110b (LOGIC BLOCK #2) and 110c (LOGIC BLOCK #3) are interconnected via a multiplexer 120 (MUX). Well known in principle to those of ordinary skill in the art, the multiplexer 120 selects either the "n" input signals on lines 115a or the "m" input signals on lines 115b based upon the state of a selection signal (not shown), and presents the selected signals (115a or 115b) on its "k" output lines 115c to the block 110c, where "k", "m", and "n" refer to a number of signals being carried on lines 115c, 115b and 115a, respectively. In the example given, "k" must be a number which is at least as large as the greater of "m" and "n". By the use of the multiplexer 120, LOGIC BLOCK #3 110c can be caused to receive signals (115a, 115b) from either LOGIC BLOCK #1 110a or LOGIC BLOCK #2 110b, at any given time. Assuming that the multiplexer 120 (MUX) is located on the integrated circuit chip close to LOGIC BLOCK #1 110a and LOGIC BLOCK #2 110b, then the area required for signal routing is reduced by limiting the number of signals (i e., "k" rather than "n+m") which must be routed to LOGIC BLOCK #3 110c.
FIG. 1b is a block diagram of a system (design) 100b employing a plurality of logic blocks 125a, 125b, 125c, and 125d interconnected by a common bus 135a. Bus buffers 130a, 130b, 130c, and 130d between the logic blocks 125a, 125b, 125c, and 125d, respectively, and the bus 135a provide means by which the logic blocks can receive data from the bus 135a and place data on the bus 135a. The bus buffers 130a, 130b, 130c, and 130d are designed and controlled such that only one bus buffer will drive (place data on) the bus 135a at and time. The logic blocks associated with the bus buffers (130a, 130b, 130c, or 130d) which are not driving the-bus can receive the data which is being driven onto the bus. By bussing groups of common signals between logic blocks, wiring efficiency is improved as compared to providing discrete non-shared connections between the logic blocks.
Unfortunately, large busses can still occupy a great deal of chip area, particularly when a large number of logic blocks are interconnected by the bus. Chip space must be allocated for routing the bus to each of the logic blocks. If a logic block uses the bus infrequently, then the benefit received from the chip area utilized to connect the logic block is low.
Multiplexing and bus-connection techniques are effective in reducing the number of signal connections between logic blocks, but are largely ineffective in improving either information efficiency or utilization of the signal wires themselves. For example, for slowly changing digital signals (i.e., digital signals which change state only infrequently), information is conveyed only when the signals change from one state to the another (i.e., if the state of a signal is already known, then there is no significant benefit in retransmitting the state of the signal until it changes state). Since the bus connections and multiplexed connections described above are static connections (i.e., fixed) they occupy space but provide no benefit when they are idle (i.e., when the signal values carried thereon are unchanging). The following U.S. Pat. Nos. are incorporated by reference herein: 4,639,620; 4,755,765; 4,855,999; 4,939,729; 5,012,126; 5,045,714; 5,241,224; and 5,260,610.